MPC8540 datasheet(1216/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-4

Freescale Semiconductor

Revision History

5.5, 5-13

Prior to Section 5.5.1, insert a new section, “Initial Instruction Fetch,”

consisting of the following text (former Section 5.5.1 now becomes

Section 5.5.2.):

“The e500 core begins execution at fixed virtual address 0xFFFF_FFFC.

The MMU has a default page translation which maps this to the identical

physical address. So, the instruction at physical address 0xFFFF_FFFC

must be a branch to another address within the 4-Kbyte boot page.”

5.6, 5-18

Remove the registers IAC3 and IAC4 from Figure 5-6.

5.14, 5-33

In Table 5-8, replace the HID1 implementation description of HID1[RFXE]

with the following:

6.1.1, 6-2

IAC3 and IAC4 are not supported and should be removed from Figure 6-1.

HID1[RFXE] controls whether assertion of core_fault_in causes a machine check interrupt. Assertion of core_fault_in

can result from uncorrectable data error, such as an L2 multibit ECC error. It can also occur for a system error if logic

on the integrated device signals a fault for nonfatal errors (read data is corrupt (or zero), but the transaction can

complete without corrupting other system state, making it unnecessary to take a machine check (for example, a master

abort of a PCI transaction).

If RFXE is 0, and core_fault_in is asserted, any data on the CCB is dropped, either stalling the load/store unit and

causing the e500 pipeline to stall until an interrupt occurs (typically generated by the programmable interrupt controller

(PIC) in response to the fault) or allowing processingþto continue with the bad data until the interrupt occurs. Because

core_fault_in cannot cause a machine check if RFXE is 0, it is critical that the system be configured to generate the

appropriate interrupt, as described below.

It is also possible to hang the processor (requiring a hard reset to recover) if a guardedþload hits in the L2 cache and

gets an uncorrectable ECC error. Because of this, avoid defining memory as cacheable but guarded. If this

combination is required, RFXE must be enabled, in which case an error causes both a machine check interrupt and

an external interrupt when a bus fault condition is detected unless interrupts are masked for all sources of bus faults.

If RFXE is 0, conditions that cause the assertion of core_fault_in cannot directly cause the e500 to generate a machine

check; however, PowerQUICC III devices must be configured to detect and enable such conditions. The following

describes how error bits should be configured:

• ECM mapping errors: EEER[LAEE] must be set. See Section 8.2.1.4, “ECM Error Enable Register (EEER).”

• L2 multiple-bit ECC errors: L2ERRDIS[MBECCDIS] must be cleared to ensure that error can be detected.

L2ERRINTEN[MBECCINTEN] must be set. SeeSection 7.3.1.5, “L2 Error Registers.”

• DDR multiple-bit ECC errors. ERR_DISABLE[MBED] and ERR_INT_EN[MBEE] must be zero and

DDR_SDRAM_CFG[ECC_EN] must be one to ensure that an interrupt is generated. See Section 9.4.1, “Register

Descriptions.”

• PCI. The appropriate parity detect and master-abort bits in ERR_DR must be cleared and the corresponding enable

bits in ERR_EN must be set to ensure that an interrupt is generated. Section 16.3.1.4, “PCI/X Error Management

Registers.”

• Local bus controller parity errors. LTEDR[PARD] must be cleared and LTEIR[PARI] must be set to ensure that an

parity errors can generate an interrupt. See Section 13.3.1.11, “Transfer Error Check Disable Register (LTEDR),”

and Section 13.3.1.12, “Transfer Error Interrupt Enable Register (LTEIR).”

• RapidIO. PCR[CCE] must be set to ensure that an interrupt is generated due to a CRC error. See

Section 17.3.2.1.2, “Port Configuration Register (PCR).”

RFXE must also be set if software requires that code execution stop immediately when a bus fault occurs rather than

continuing with the bad data until the interrupt arrives. Again, this results in both a machine check interrupt and an

external interrupt when a bus fault is detected, unless all possible sources for bus fault have their interrupts

masked.þThe machine check interrupt can then reenable normal interrupts and wait for the interrupt due to the fault to

be received before returning from the machine check.

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