MPC8540 datasheet(1213/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-1

Appendix A

Revision History

This appendix provides a list of the major differences between revisions of the MPC8540

PowerQUICC III Integrated Host Processor Reference Manual, Revision 0 and MPC8540

PowerQUICC III Integrated Host Processor Reference Manual, Revision 1.

A.1

Changes From Revision 0 to Revision 1

Major changes to the MPC8540 PowerQUICC III Integrated Host Processor Reference Manual

between Revision 0 to Revision 1 are as follows:

Section, Page

Changes

Chapters 4, 16, 18, 20

Throughout all applicable chapters, correctly state the debug mode source ID

(formerly documented to be visible on signals PCI_AD[63:59]) to be visible on

signals PCI_AD[62:58].

2.4, 2-18

In Table 2-9, correct the reset value for the I2CDFSRR register to be 0x10.

2.4, 2-27

In Table 2-9, add the following rows under the TSEC1 FIFO Control and

Status Registers section:

2.4, 2-27

In Table 2-9, correct the reset value for the OSTBD register to be

0x0800_0000.

2.4, 2-28

In Table 2-9, correct the MACCFG1 register from having R/W, R access to

R/W access.

2.4, 2-28

In Table 2-9, correct the reset value for the IFSTAT register to be

0x0000_0000.

2.4, 2-31

In Table 2-9, correct the CAR1 and CAR2 registers from having R access

to R/W access.

Also, remove the “Cleared on read” footnote designation from the CAR1

and CAR2 registers.

0x2_404C

FIFO_PAUSE_CTRL—FIFO pause control register

R/W

0x0000_0000

14.5.3.2.1/14-30

0x2_4050–

0x2_4088

Reserved

0x0000_0000

—

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