MPC8540 datasheet(1209/1302 Pages) FREESCALE

1209 / 1302 page

Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-69

21.6.4 Data Extraction to the L2 Cache

Some applications require the ability to identify selected portions of data within a frame’s data

payload. This process is called extraction although the data is not truly removed. Rather than

literarily extracting a section of the data and copying it into a new memory location, the data is

placed in the L2 cache. This allows the processor to quickly access critical frame information as

soon as the processor is ready without having to first fetch the data from main memory. This

reduction in latency can result in a substantial improvement in packet processing throughput.

Extraction functionality is controlled and configured with ATTR and ATTRELI. See

Section 21.5.3.8.1, “Attribute Register (ATTR),” and Section 21.5.3.8.2, “Attribute Extract

Length and Extract Index Register (ATTRELI),” for specific register information.

21.7 Application Information

21.7.1 Interface Mode Configuration

This section describes how to configure the FEC in the MII mode. The pinout, the data registers

that must be initialized, as well as speed selection options are described.

Offset + 2 0–15

Data

Length

Data length. Written by the FEC.

Data length is the number of octets written by the FEC into this BD’s data buffer if L is

cleared (the value is equal to MRBL), or the length of the frame including CRC, if L is set.

Offset + 4 0–31

Rx Data

Buffer

Pointer

Receive buffer pointer. Written by user.

The receive buffer pointer, which always points to the first location of the associated data

buffer, must be 64-byte aligned. The buffer must reside in memory external to the FEC.

Table 21-49. Receive Buffer Descriptor Field Descriptions (continued)

Offset

Bits

Name

Description

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