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MPC8540 Datasheet(PDF) 1207 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1207 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
21-67
21.6.3.2 Receive Buffer Descriptor (RxBD)
In the RxBD the user initializes the E, I, and W bits in the first word and the pointer in second
word. If the data buffer is used, the FEC modifies the E, L, F, M, BC, MC, LG, NO, SH, CR, OV,
and TR bits and writes the length of the used portion of the buffer in the first word. The M, BC,
MC, LG, NO, SH, CR, OV, and TR bits in the first word of the buffer descriptor are modified by
the FEC only if the L bit is set. The first word of the RxBD contains control and status bits.
Figure 21-47 describes the RxBD.
Table 21-49 describes the fields of the RxBD.
Offset + 0
15
TXTRUNC TX truncation. Set in the last TxBD (TxBD[L] is set) when IEVENT[BABT] occurs
for the frame.
Offset + 2
0–15
Data
Length
Data length is the number of octets the FEC transmits from this BD’s data buffer.
It is never modified by the FEC. This field must be greater than zero. This field
must be greater than zero.
Offset + 4
0–31
TX Data
Buffer
Pointer
The transmit buffer pointer contains the address of the associated data buffer.
There are no alignment requirements for this address.
0123456
789
10
11
12
13
14
15
Offset + 0
E
RO1
W
I
L
F
0
M
BCMCLG
NO
SH
CROV
TR
Offset + 2
DATA LENGTH
Offset + 4
RX DATA BUFFER POINTER
Offset + 6
Figure 21-47. Receive Buffer Descriptor
Table 21-49. Receive Buffer Descriptor Field Descriptions
Offset
Bits
Name
Description
Offset + 0
0
E
Empty. Written by the FEC (when cleared) and by the user (when set).
0 The data buffer associated with this BD is filled with received data, or data reception
is aborted due to an error condition. Status and length fields have been updated as
required.
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Offset + 0
1
RO1
Receive software ownership bit.
This field is reserved for use by software. This read/write bit is not modified by hardware,
nor does its value affect hardware.
Offset + 0
2
W
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in RBASE.
Table 21-48. Transmit Data Buffer Descriptor (TxBD) Field
Descriptions (continued)
Offset
Bits
Name
Description



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