MPC8540 datasheet(1214/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-2

Freescale Semiconductor

Revision History

2.4, 2-32

In Table 2-9, add the following two rows under “FIFO Control and Status

Registers”:

2.4, 2-35

In Table 2-9, correct the ATTR and ATTRELI registers from having R

access to R/W access.

2.4, 2-35

In Table 2-9, correct the offset for the Reserved addresses after the EOI

2.4, 2-47

In Table 2-9, correct the reset value for the GPINDR register to be

0xnnnn_0000.

2.4, 2-48

In Table 2-9, correct the name of the register with offset 0xE_1094 from

PMLCB5 to PMLCB8.

2.4, 2-42–46

In Table 2-9, correct the access designation for all RapidIO Registers listed

as “Special” to read “R/W”.

4.3.1.3, 4-7

Replace the second sentence of the first paragraph to read:

“The first instruction executed by the e500 core is always address

0xFFFF_FFFC, which must be a branch to an address within the 4-Kbyte

boot page.”

4.4.3.3, 4-13

Insert the following sentence at the start of the first paragraph:

“The first instruction executed by the e500 core is always address

0xFFFF_FFFC, which must be a branch to an address within the 4-Kbyte

boot page.”

4.4.3.3, 4-14

Add the following sentence to the end of the last paragraph:

“If enabled, this translation only affects CPU accesses to 0xFFFF_Fnnn.”

4.4.4.1, 4-22

Append the end of the first paragraph of Section 4.4.4.1, with the following

sentence:

“Note that the divide-by-two CCB clock divider and the divide-by-n CCB

clock divider, shown in Figure 4-6, are located in the DDR and local bus

blocks, respectively.”

0x2_604C

FIFO_PAUSE_CTRL—FIFO pause control

R/W

0x0000_0000

21.5.3.2.1/21-22

0x2_6050–

0x2_6088

Reserved

0x0000_0000

—

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