MPC8540 datasheet(1194/1302 Pages) FREESCALE

1194 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-54

Freescale Semiconductor

10/100 Fast Ethernet Controller

recognition algorithm is complete, system bus usage is not wasted on frames not wanted by this

station.

If a frame is accepted, the Ethernet controller fetches the receive buffer descriptor (RxBD) from

the queue. If the RxBD is not being used by software (RxBD[E] is set), the FEC begins transferring

the incoming frame. RxBD[F] is set for the first RxBD used for any receive frame.

If the buffer is filled, the FEC clears RxBD[E] and generates an interrupt if RxBD[I] is set. If the

incoming frame is larger than the buffer, the Ethernet controller fetches the next RxBD in the table;

if it is empty, it continues receiving the rest of the frame. In half-duplex mode, if a collision is

detected during the frame, no RxBDs are used. Thus, no collision frames are presented to the user

except late collisions, which indicate serious LAN problems.

The RxBD length is determined by the MRBL field in the maximum receive buffer length register

(MRBLR). The smallest valid value is 64 bytes. During reception, the Ethernet controller checks

for frames that are too short or too long. When the frame ends (FEC_CRS is negated), the receive

CRC field is checked and written to the data buffer. The data length written to the last RxBD in

the Ethernet frame is the length of the entire frame, which enables the software to recognize a

frame-too-long condition.

Receive frames are not truncated if they exceed maximum frame bytes in the MAC’s maximum

frame register if MACCFG2[Huge Frame] is set, however the babbling receiver error interrupt

occurs (IEVENT[BABR] is set) and RxBD[LG] is set.

When the receive frame is complete, the Ethernet controller sets RxBD[L], updates the frame

status bits in the RxBD, and clears RxBD[E]. If RxBD[I] is set, the Ethernet controller next

generates a maskable interrupt, indicating that a frame was received and is in memory. The

Ethernet controller then waits for a new frame.

To interrupt reception, or rearrange the receive queue, DMACTRL[GRS] must be set. When this

bit is set the FEC receiver does a graceful receive stop. The Ethernet controller stops immediately

if no frames are being received or continues receiving until the current frame either finishes or an

error condition occurs. The IEVENT[GRSC] interrupt event is signalled when the graceful receive

stop operation is completed. While in this mode the user can then clear IEVENT[GRSC] and can

write to registers that are accessible to both user and the FEC hardware without fear of conflict.

When DMACTRL[GRS] is cleared, the FEC scans the input data stream for the start of a new

frame (preamble sequence and start of frame delimiter), it resumes receiving, and the first valid

frame received is placed in the next available RxBD.

21.6.2.5 Frame Recognition

The Ethernet controller performs frame recognition using destination address (DA) recognition. A

frame can be rejected or accepted based on the outcome.

MPC8540 Datasheet(PDF) 1194 Page - Freescale Semiconductor, Inc