MPC8540 datasheet(1193/1302 Pages) FREESCALE

1193 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-53

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TxBD[PAD/CRC] is set in first TxBD

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TxBD[TC] is set in first TxBD

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MACCFG2[PAD/CRC] is set

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MACCFG2[CRC EN] is set

After the FCS is sent, the Ethernet controller writes the frame status bits into the BD and clears

TxBD[R]. When the end of the current buffer is reached and TxBD[L] = 0 (a frame is comprised

of multiple buffer descriptors), only TxBD[R] is cleared.

For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The

Ethernet controller then proceeds to the next TxBD in the table. In this way, the core can be

interrupted after each frame, after each buffer, or after a specific buffer is sent. If

TxBD[PAD/CRC] = 1, the Ethernet controller pads any frame shorter than 64 bytes.

To pause transmission, or rearrange the transmit queue, set DMACTRL[GTS]. This can be useful

for transmitting expedited data ahead of previously linked buffers or for error situations. When this

bit is set the FEC transmitter performs a graceful transmit stop. The Ethernet controller stops

immediately if no transmission is in progress or continues transmission until the current frame

either finishes or terminates with an error. The IEVENT[GTSC] interrupt occurs when the graceful

transmit stop operation is completed. When DMACTRL[GTS] is cleared, the FEC resumes

transmission with the next frame.

The FEC sends bytes least-significant nibble first and each nibble is sent least-significant bit first.

21.6.2.4 FEC Frame Reception

The FEC Ethernet receiver is designed to work with almost no core intervention and can perform

address recognition, CRC checking, short frame checking, and maximum frame-length checking.

The receiver can also force frame headers and buffer descriptors to be allocated into the L2 cache.

See Section 21.6.4, “Data Extraction to the L2 Cache” for additional information.

After a hardware reset, the software driver clears the RSTAT register and sets

MACCFG1[RX_EN]; the Ethernet receiver is enabled and immediately starts processing receive

frames. The MAC checks for when FEC_RX_DV is asserted and as long as FEC_COL remains

negated (full-duplex mode ignores FEC_COL) the MAC looks for the start of a frame by searching

for a valid preamble/SFD (start of frame delimiter) header, which is stripped, and the frame begins

to be processed. If a valid header is not found, the frame is ignored.

If the receiver detects the first bytes of a frame, the FEC begins to perform the frame recognition

function through destination address (DA) recognition. (See Section 21.6.2.5, “Frame

Recognition” for additional information.) Based on this match the frame can be accepted or

rejected. Once accepted, the FEC processes the frame based on user-defined attributes.

The receiver can also filter frames based on physical (individual), group (multicast), and broadcast

addresses. Because Ethernet receive frame data is not written to memory until the internal frame

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