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MPC8540 Datasheet(PDF) 1189 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1189 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
21-49
Figure 21-42. FEC–MII Connection
An MII interface has 16 signals, as defined by the IEEE 802.3u standard, for connecting to an
Ethernet PHY. Table 21-41 lists the MII interface signals.
21.6.2 FEC Channel Operation
This section describes the operation of the FEC. First the software initialization sequence is
described. Next, the software (Ethernet driver) interface for transmitting and receiving frames is
described. Address recognition and hash table algorithm features are also discussed. The section
concludes with interrupt handling, inter-packet gap time, and loop-back descriptions.
Table 21-41. MII Interface Signals
Frequency [MHz] 25
Voltage [V] 3.3
Signals
I/O
No. of Signals
Signals
I/O
No. of Signals
FEC_TX_CLK
I
1
FEC_RxD[0]
I
1
FEC_TxD[0]
O
1
FEC_RxD[1]
I
1
FEC_TxD[1]
O
1
FEC_RxD[2]
I
1
FEC_TxD[2]
O
1
FEC_RxD[3]
I
1
FEC_TxD[3]
O
1
FEC_RX_DV
I
1
FEC_TX_EN
O
1
FEC_RX_ER
I
1
FEC_TX_ER
O
1
FEC_COL
I
1
FEC_RX_CLK
I
1
FEC_CRS
I
1
Transmit Error (FEC_TX_ER)
Transmit Data (FEC_TXD[3:0])
Transmit Enable (FEC_TX_EN)
Transmit Clock (FEC_TX_CLK)
Collision Detect (FEC_COL)
Receive Data (RXD[3:0])
Receive Error (FEC_RX_ER)
Receive Clock (FEC_RX_CLK)
Receive Data Valid (FEC_RX_DV)
Carrier Sense Output (FEC_CRS)
10/100
Medium
10/100
Controller
Controller
PHY



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