MPC8540 datasheet(1188/1302 Pages) FREESCALE

1188 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-48

Freescale Semiconductor

10/100 Fast Ethernet Controller

Table 21-40 describes the fields of the ATTRELI register.

21.6 Functional Description

This section describes many of the functions of the 10/100 fast Ethernet controller (FEC).

21.6.1 Connecting to the Physical Interface

This section describes how to connect the FEC to the MII interface. The bus follows the bus

conventions used in the IEEE 802.3 specification because the PHY follows the same conventions

(that is, in the bus TXD[3:0], bit 3 is the MSB and bit 0 the LSB).

21.6.1.1 Media-Independent Interface (MII)

This section describes the media independent interface (MII) intended to be used between the

PHYs and the FEC. Figure 21-42 depicts the basic components of the MII including the signals

required to establish the FEC module connection with a PHY.

15 16 17 18

RESET

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6BFC

Figure 21-41. ATTRELI Register Definition

Table 21-40. ATTRELI Field Descriptions

Bits

Name

Description

0–1

—

Reserved

2–15

Extracted length. Specifies the number of bytes to extract from the receive frame. The DMA controller

uses this field to perform extraction. If set to zero, no extraction is performed.

16–17

—

Reserved

18–31

Extracted index. Points to the first byte within the receive frame from which to begin extracting data.

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