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MPC8540 Datasheet(PDF) 1184 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1184 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
21-44
Freescale Semiconductor
10/100 Fast Ethernet Controller
user reads MACSTNADDR1, 0xCDAB7856 is returned. A read of MACSTNADDR2 returns a
value of 0x34120000. Note that the I/G and U/L bits of the frame’s DA field are located at the lsbs
of the 1st octet stored in MACSTNADDR2, where the I/G bit is bit 15, and the U/L bit is bit 14.
Table 21-35 describes the fields of the MACSTNADDR1 register.
21.5.3.6.8 Station Address Register Part 2 (MACSTNADDR2)
The MACSTNADDR2 register is written by the user. Figure 21-37 describes the
MACSTNADDR2 register. Note that the I/G and U/L bits of the frame’s DA field are located at
the lsbs of the 1st octet stored in MACSTNADDR2, where the I/G bit is bit 15, and the U/L bit is
bit 14.
07
8
15 16
23 24
31
R
Station Address, 6th Octet Station Address, 5th Octet Station Address, 4th Octet Station Address, 3rd Octet
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x2_6540
Figure 21-36. Station Address Part 1 Register Definition
Table 21-35. MACSTNADDR1 Field Descriptions
Bit
Name
Description
0–7
Station Address, 6th Octet This field holds the sixth octet of the station address. The sixth octet (station
address bits 40–47) defaults to a value of 0x00.
8–15
Station Address, 5th Octet This field holds the fifth octet of the station address. The fifth octet (station address
bits 32–39) defaults to a value of 0x00.
16–23 Station Address, 4th Octet This field holds the fourth octet of the station address. The fourth octet (station
address bits 24–31) defaults to a value of 0x00.
24–31 Station Address, 3rd Octet This field holds the third octet of the station address. The third octet (station
address bits 16–23) defaults to a value of 0x00.
07
8
15 16
31
R
Station Address, 2nd
Octet
Station Address, 1st Octet
000000
0000000000
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x2_6544
Figure 21-37. Station Address Part 2 Register Definition



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