MPC8540 datasheet(1180/1302 Pages) FREESCALE

1180 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-40

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.5.3.6.2 MAC Configuration Register 2 (MACCFG2)

The MACCFG2, shown in Figure 21-31, is written by the user.

Table 21-30 describes the fields of the MACCFG2 register.

0 0

Reset

0000_0000_0000_0000

20 21

24 25

Preamble_Length

I/F_Mode

Huge Frame Length_Check

PAD/CRC CRC EN Full_Duplex

Reset

0111_0000_0000_0000

Offset

0x2_6504

Figure 21-31. MACCFG2 Register Definition

Table 21-30. MACCFG2 Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–19

Preamble_Length This field determines the length in bytes of the preamble field of the packet. Its default is

0x7. A preamble length of 0 is not supported.

20–21

—

Reserved

22–23

I/F_Mode

Determines the type of interface the MAC is connected to.

00 Reserved

01 Nibble mode (MII)

10 Reserved

11 Reserved

24–25

—

Reserved

Huge Frame

0 Default. The MAC limits the length of frames at the MAXIMUM FRAME LENGTH value.

1 Frames longer than the MAXIMUM FRAME LENGTH can be transmitted and received.

Length_Check

0 Default. Clear this bit if no length field checking is desired.

1 The MAC checks the frame’s length field to ensure it matches the actual data field

length.

—

Reserved

PAD/CRC

0 Default. Transmitted short frames are not padded.

1 The MAC pads all transmitted short frames and appends a CRC to every frame whether

or not padding was required.

CRC EN

CRC enable

0 Default. Clear if frames presented to the MAC have a valid length and contain a valid

CRC.

1 Causes the MAC to append a CRC on all frames. If the configuration bit PAD/CRC or

the per-packet PAD/CRC is set, CRC EN is ignored.

Full_Duplex

0 Default. Clearing this bit configures the MAC to operate in half-duplex mode only.

1 Configures the MAC to operate in full-duplex mode.

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