MPC8540 datasheet(1179/1302 Pages) FREESCALE

1179 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-39

Reset_Tx_MC

0 Default

1 Setting this bit puts the PETMC transmit MAC control block in reset. This block

multiplexes data and control frame transfers. It also responds to XOFF PAUSE control

frames.

Reset_Rx_Fun

0 Default

1 Setting this bit puts the receive function block in reset. This block performs the receive

frame protocol.

Reset_Tx_Fun

0 Default

1 Setting this bit puts the transmit function block in reset. This block performs the frame

transmission protocol.

16–22

—

Reserved

Loop_Back

0 Default.

1 Causes the MAC transmit outputs to be looped back to the MAC receive inputs.

24–25

—

Reserved

Rx_Flow

0 Default. The receive MAC control ignores PAUSE flow control frames.

1 The receive MAC control can detect and act on PAUSE flow control frames.

Tx_Flow

0 Default. The transmit MAC control cannot send flow control frames.

1 The transmit MAC control can send PAUSE flow control frames when requested by the

system.

Sync’d_Rx_EN Receive enable synchronized to the receive stream. (Read only)

0 Frame reception is not enabled.

1 Frame reception is enabled.

Rx_EN

Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set

DMACTRL[GRS] then confirm subsequent occurrence of the graceful receive stop interrupt

(IEVENT[GRSC] is set).

0 Default. The MAC cannot receive frames from the PHY.

1 The MAC can receive frames from the PHY.

Sync’d_Tx_EN

Transmit enable synchronized to the transmit stream. (Read only)

0 Frame transmission is not enabled.

1 Frame transmission is enabled.

Tx_EN

Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set

DMACTRL[GTS] then confirm subsequent occurrence of the graceful transmit stop

interrupt (IEVENT[GTSC] is set).

0 Default. Clearing this bit prevents the transmission of frames.

1 Setting this bit allows the MAC to transmit frames from the system.

Table 21-29. MACCFG1 Field Descriptions (continued)

Bits

Name

Description

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