MPC8540 datasheet(1183/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-43

Table 21-33 describes the fields of the MAXFRM register.

21.5.3.6.6 Interface Status Register (IFSTAT)

Figure 21-35 shows the IFSTAT register.

Table 21-34 describes the fields of the IFSTAT register.

21.5.3.6.7 Station Address Register Part 1 (MACSTNADDR1)

The MACSTNADDR1 register is written by the user. Figure 21-36 describes the

MACSTNADDR1 register. The value of the station address written by the user into

MACSTNADDR1 and MACSTNADDR2 is byte-reversed from how it would appear in the DA

field of a frame in memory. For example, for a station address of 0x12345678ABCD, perform a

write to MACSTNADDR1 of 0xCDAB7856, and to MACSTNADDR2 of 0x34120000. When the

Table 21-33. MAXFRM Descriptions

Bit

Name

Description

0–15

—

Reserved

16–31

Maximum Frame Sets the maximum frame size in both the transmit and receive directions. (Refer to

MACCFG2[Huge Frame].)

00 00 000 000 000 000 00 000

0Excess Defer 0

000

Link

Fail

00 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_653C

Figure 21-35. Interface Status Register Definition

Table 21-34. IFSTAT Field Descriptions

Bit

Name

Description

0–21

—

Reserved

Excess

Defer

Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared

by default.

0 Normal operation

1 The MAC excessively defers a transmission.

23–27

—

Reserved

Link Fail

Link Fail. This bit indicates the status of signal detection.

0 The100X module has detected a “signal detect” for longer than 330 mS.

1 The100X module has detected a “signal detect” for less than 330 mS or not at all.

29–31

—

Reserved

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