MPC8540 datasheet(1186/1302 Pages) FREESCALE

1186 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-46

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.5.3.7.2 Group Address Registers 0–7 (GADDRn)

The GADDRn registers, shown in Figure 21-39, represent 256 entries of the group (multicast)

address hash table used in the address recognition process. When the DA field of a receive frame

is processed through a 32-bit CRC generator, the 8-bit MSB of the CRC remainder is mapped to

one of the 256 entries. The user can enable a hash entry by setting the appropriate bit. A hash table

hit occurs when the DA CRC result points to an enabled hash entry.

Table 21-38 describes the field of the GADDRn registers.

21.5.3.8 Attribute Registers

This section describes the two FEC frame attribute registers.

21.5.3.8.1 Attribute Register (ATTR)

The ATTR, shown in Figure 21-40, defines attributes and transaction types used to access buffer

descriptors and to write receive data and to read transmit data. Snoop enable attributes may be set

for reading buffer descriptors and for reading transmit data. Buffer descriptors may be written with

attributes that cause allocation into the L2 cache with or without line locking. Similarly, sections

of a receive frame header may have attributes attached that cause allocation and locking in the L2

cache. This process of specifying a region of each frame to stash into the L2 cache is referred to

as extraction. Extraction is specified in conjunction with ATTRELI. ATTR[ELCWT] only has

meaning if the ATTRELI[EL] field is non-zero.

GADDRn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6880, 0x2_6884, 0x2_6888, 0x2_688C, 0x2_6890, 0x2_6894, 0x2_6898, 0x2_689C

Figure 21-39. GADDRn Register Definition

Table 21-38. GADDRn Field Description

Bits

Name

Description

0–31

GADDRn Represents the 32-bit value associated with the corresponding register. GADDR0 contains the

high-order 32 bits of the 256-entry group hash table and GADDR7 represents the low-order 32 bits.

For instance, the MSB of GADDR0 correlates to entry 0 and the LSB of GADDR7 correlates to

entry 255.

MPC8540 Datasheet(PDF) 1186 Page - Freescale Semiconductor, Inc