MPC8540 datasheet(1187/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-47

Table 21-39 describes the fields of the ATTR register.

21.5.3.8.2 Attribute Extract Length and Extract Index Register (ATTRELI)

The ATTRELI registers are written by the user to specify the extract index and extract length.

Figure 21-41 describes the definition for ATTRELI.

15 1617

1819

22 23

0000_0000_0000_0000

ELCWT

BDLWT

RDSEN RBDSEN

0 000 00

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6BF8

Figure 21-40. ATTR Register Definition

Table 21-39. ATTR Field Descriptions

Bits

Name

Description

0–16

—

Reserved

17–18

ELCWT

Extracted L2 cache write type. Specifies the write transaction type to perform for the extracted

data. This occurs only if ATTRELI[EL] is non-zero. For maximum performance, it is recommended

that if ELCWT is set to allocate, BDLWT also be set to allocate. Writes to cache are always

performed with snoop. This setting overrides the RDSEN bit setting.

00 No allocation performed.

01 Reserved, no extraction occurs.

10 Allocate L2 cache line.

11 Allocate and lock L2 cache line.

—

Reserved

20–21

BDLWT

Buffer descriptor L2 cache write type. Specifies the write transaction type to perform for the buffer

descriptor for a receive frame. Writes to cache are always performed with snoop.

00 No allocation performed. This setting overrides the RBDSEN bit setting.

01 Reserved

10 Allocate L2 cache line.

11 Allocate and lock L2 cache line.

22–23

—

Reserved

RDSEN

Rx data snoop enable. This bit is superseded by the ELCWT settings.

0 Disables snooping of all receive frames data to memory unless ELCWT specifies L2 allocation.

1 Enables snooping of all receive frames data to memory.

RBDSEN RxBD snoop enable. This bit is superceded by the BDLWT settings.

0 Disables snooping of all receive BD memory accesses unless BDLWT specifies L2 allocation.

1 Enables snooping of all receive BD memory accesses.

26–31

—

Reserved

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