MPC8540 datasheet(1191/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-51

4. Clearing DMACTRL[GTS] triggers the transmission of frame data if the transmitter had

been previously stopped. DMACTRL[GRS] must be cleared if the receiver was

previously stopped. See Section 21.5.3.1.6, “DMA Control Register (DMACTRL),” and

Section 21.6.3.1, “Transmit Data Buffer Descriptor (TxBD).”

21.6.2.2 Soft Reset and Reconfiguring Procedure

Before issuing a soft-reset to and/or reconfiguring the MAC with new parameters, the user must

properly shutdown the DMA and make sure it is in an idle state for the entire duration. The user

must gracefully stop the DMA by setting both GRS and GTS bits in the DMACTRL register, then

wait for both GRSC and GTSC bits to be set in the IEVENT register before resetting the MAC or

changing parameters. Both GRS and GTS bits must be cleared before re-enabling the MAC to

resume the DMA.

During the MAC configuration, if a new set of Tx buffer descriptors are used, the user must load

the pointers into the TBASE register. Likewise if a new set of Rx buffer descriptors are used, the

RBASE register must be written with the new pointer.

Following is a procedure to gracefully reset and reconfigure the MAC:

1. Set GTS bit in DMACTRL register.

2. Poll GTSC bit in IEVENT register until detected as set.

3. Clear both Rx_EN and Tx_EN bits in MACCFG1.

4. Wait for a period of 9.6 Kbytes worth of data on the interface (~8ms worst case).

5. Set GRS bit in DMACTRL register.

6. Poll GRSC bit in IEVENT register until detected as set.

7. Set Soft_Reset bit in MACCFG1 register.

8. Clear Soft_Reset bit in MACCFG1 register.

9. Load TBASE with new TxBD pointer.

10. Load RBASE with new RxBD pointer.

11. Set up other MAC registers (MACCFG2, MAXFRM, and so on).

12. Set WWR and WOP bits in DMACTRL register.

13. Clear THLT bit in TSTAT register and QHLT bit in RSTAT register by writing 1 to these

bits.

14. Clear GRS/GTS bits in DMACTRL. (Do not change other bits.)

15. Enable Tx_EN/Rx_EN in MACCFG1 register.

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