MPC8540 datasheet(1192/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-52

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.6.2.3 FEC Frame Transmission

The Ethernet transmitter requires almost no core intervention. After the software driver initializes

the system, the FEC begins to poll the first TxBD in the TxBD ring every 512 transmit clocks. If

TxBD[R] is set, the FEC begins moving transmit buffer from memory to its Tx FIFO. The

transmitter takes data from the Tx FIFO and transmits data to the MAC. The MAC transmits the

data through the MII interface to the physical media. The transmitter, once initialized, runs until

the end-of-frame (EOF) condition is detected unless a collision within the collision window occurs

(half-duplex mode) or an abort condition is encountered.

If the user has a frame ready to transmit, a transmit-on-demand function may be emulated while

in polling mode by using the graceful-transmit-stop feature. First, clear the IMASK[GTSCEN] bit

to mask the graceful-transmit-stop complete interrupt. Next set, then immediately clear the

DMACTRL[GTS] bit. Clear the resulting IEVENT[GTSC] bit. Finally, the IMASK[GTSCEN] bit

may be set once again.

There is one internal buffer for out-of-sequence flow control frames. When the FEC is between

frames, this buffer is polled. The buffer must contain the whole frame. Once the FEC is in paused

mode, the out-of-sequence buffer descriptor cannot be used to send another flow control frame

because the MAC treats it like a regular TxBD.

In half-duplex mode (MACCFG2[Full_Duplex] = 0) the MAC defers transmission if the line is

busy (FEC_CRS asserted). Before transmitting, the MAC waits for carrier sense to become

inactive, at which point it then determines if FEC_CRS remains negated for 60 clocks. If so,

transmission begins after an additional 36 bit times (96 bit times after FEC_CRS originally

became negated). If FEC_CRS continues to be asserted, the MAC follows a specified back-off

procedure and tries to retransmit the frame until the retry limit is reached. Data stored in the Tx

FIFO is retransmitted in case of a collision. This improves bus usage and latency.

The transmitter also monitors for an abort condition and terminates the current frame if an abort

condition is encountered. In full-duplex mode the protocol is independent of network activity, and

only the transmit inter-frame gap needs to be enforced.

The transmit block also implements full-duplex flow control. If a flow control frame is received,

the MAC does not service the transmitter’s request to send data until the pause duration is over. If

the MAC is currently sending data while a pause frame is received, the MAC finishes sending the

current frame, then suspends subsequent frames (except a pause frame) until the pause duration is

over. The pause duration is defined by the received pause control frame and begins when the frame

was first received. In addition, the transmitter supports transmission of flow control frames via

TCTRL[TFC_PAUSE]. The transmit pause frame is generated internally based on the PAUSE

the pause timer has not expired.

The MAC automatically appends FCS (32-bit CRC) bytes to the frame if any of the following

values are set:

MPC8540 Datasheet(PDF) 1192 Page - Freescale Semiconductor, Inc