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MPC8540 Datasheet(PDF) 1190 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1190 Page - Freescale Semiconductor, Inc |
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1190 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 21-50 Freescale Semiconductor 10/100 Fast Ethernet Controller 21.6.2.1 Initialization Sequence This section describes which registers are reset due to a hard or software reset and what registers the user must initialize before the FEC is enabled. 21.6.2.1.1 Hardware Controlled Initialization A hard reset occurs when the system powers up. All of the FEC’s registers and control logic are reset to their default states after a hard reset has occurred. 21.6.2.1.2 User Initialization After the system has undergone a hard reset, software must initialize certain basic FEC registers. Other registers can also be initialized during this time, but they are optional and must be determined based on the requirements of the system. See Table 21-2 for the register list. Table 21-42 describes the minimum steps for register initialization. After the registers are initialized, the user must execute the following steps in the order described below to bring the FEC into a functional state (out of reset): 1. For the transmission of Ethernet frames, TxBDs have to be first built in memory, linked together as a ring, and pointed to by the TBASE register. At least two buffer descriptors per ring are required. Setting the ring size to one causes the same frame to be sent twice. 2. Likewise, for the reception of Ethernet frames, the receive queue must be ready, with its RxBD pointed to by the RBASE register. Both transmit and receive can be gracefully stopped after transmission and reception begins. 3. Write to the MACCFG1 register and set the appropriate bits. These must include RX_EN = 1, and TX_EN = 1. To enable flow control, Rx_Flow and Tx_Flow must also be set. Table 21-42. Steps of Minimum Register Initialization Description 1. Set, then clear MACCFG1 [Soft_Reset] 2. Initialize MACCFG2 3. Initialize MAC station address 4. Set up the PHY using the MII Mgmt Interface 5. Clear IEVENT 6. Initialize IMASK 7. Initialize IADDRn 8. Initialize GADDRn 9. Initialize RCTRL 10. Initialize DMACTRL |
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