MPC8540 datasheet(1185/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-45

Table 21-36 describes the fields of the MACSTNADDR2 register.

21.5.3.7 Hash Function Registers

This section provides detailed descriptions of the registers used for hash functions. All of the

registers are 32 bits wide. When the DA field of a receive frame is processed through a 32-bit CRC

generator, the 8-bit MSB of the CRC remainder is mapped to a hash table entry. The user can

enable a hash entry by setting the appropriate bit. A hash entry usually represents a set of

addresses. A hash table hit occurs when the DA CRC result points to an enabled hash entry. The

user must further filter the address. See Section 21.6.2.5.2, “Hash Table Algorithm,” for more

information on the hash algorithm.

21.5.3.7.1 Individual Address Registers 0–7 (IADDRn)

The IADDRn registers, shown in Figure 21-38, represent 256 entries of the individual (unicast)

address hash table used in the address recognition process. When the DA field of a receive frame

is processed through a 32-bit CRC generator, the 8 high-order bits (0–7) of the CRC remainder are

mapped to one of the 256 entries. The user can enable a hash entry by setting the appropriate bit.

A hash table hit occurs when the DA CRC result points to an enabled hash entry.

Table 21-37 describes the field of the IADDRn registers.

Table 21-36. MACSTNADDR2 Field Descriptions

Bit

Name

Description

0–7

Station Address, 2nd Octet This field holds the second octet of the station address. The second octet (station

address bits 8–15) defaults to a value of 0x00.

8–15

Station Address, 1st Octet This field holds the first octet of the station address. The first octet (station address

bits 0–7) defaults to a value of 0x00.

16–3

—Reserved

IADDRn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6800, 0x2_6804, 0x2_6808, 0x2_680C, 0x2_6810, 0x2_6814, 0x2_6818, 0x2_681C

Figure 21-38. IADDRn Register Definition

Table 21-37. IADDRn Field Description

Bits

Name

Description

0–31

IADDRn

Represents the 32-bit value associated with the corresponding register. IADDR0 contains the

high-order 32 bits of the 256-entry hash table and IADDR7 represents the low-order 32 bits. For

instance, the MSB of IADDR0 correlates to entry 0 and the LSB of IADDR7 correlates to entry 255.

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