MPC8540 datasheet(1176/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-36

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.5.3.5 MAC Functionality

This section describes the MAC registers and provides a brief overview of some of the

functionality that can be exercised through the use of these registers, particularly those that provide

functionality not explicitly required by the IEEE 802.3 standard. All of the MAC registers are 32

bits wide.

21.5.3.5.1 Configuring the MAC

MAC configuration registers 1 and 2 provide a way to configure the MAC as follows:

•

Adjusting the preamble length – The length of the preamble can be adjusted from the

nominal seven bytes to some other(non-zero) value.

•

Varying pad/CRC combinations – Two different pad/CRC combinations are provided to

handle a variety of system requirements. The most simple are frames that already have a

valid FCS field. In this case, the CRC is checked and reported via the transmit statistics

vector (TSV[51:0]). These options include appending a valid CRC, or padding and then

appending a valid CRC, resulting in a minimum frame of 64 octets. In addition to the

programmable register set, the pad/CRC behavior can be dynamically adjusted on a

per-packet basis.

21.5.3.5.2 Controlling CSMA/CD

The half-duplex register (HAFDUP) controls the carrier-sense multiple access/collision detection

(CSMA/CD) logic. After a packet is sent, the device begins timing the inter-packet gap (IPG) as

programmed in the back-to-back IPG configuration register. The system is then free to begin

another frame transfer.

In full-duplex mode, the carrier sense (FEC_CRS) and collision (FEC_COL) indications from the

PHY are ignored, but in half-duplex mode, the FEC defers to FEC_CRS and, following a carrier

event, times the IPG using the non–back-to-back IPG configuration values that include support for

the optional two-thirds, one-third FEC_CRS deferral process. This optional IPG mechanism

enhances system robustness and ensures fair access to the medium. During the first two-thirds of

the IPG, the IPG timer is cleared if FEC_CRS is sensed. During the final one-third of the IPG,

FEC_CRS is ignored and the transmission begins when IPG is timed. The two-thirds/one-third

ratio is recommended.

21.5.3.5.3 Handling Packet Collisions

When transmitting a packet in half-duplex mode, the FEC is sensitive to FEC_COL. If a collision

occurs, it aborts the packet and outputs the 32-bit jam sequence. The jam sequence is made up of

several bits of the CRC, inverted to guarantee an invalid CRC upon reception. A signal is sent to

the system indicating a collision occurred and the start of the frame is needed for retransmission.

The FEC then backs-off of the medium for a time determined by the truncated binary exponential

MPC8540 Datasheet(PDF) 1176 Page - Freescale Semiconductor, Inc