MPC8540 datasheet(1172/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-32

Freescale Semiconductor

10/100 Fast Ethernet Controller

Table 21-22 describes the fields of the RCTRL register.

21.5.3.4.2 Receive Status Register (RSTAT)

The FEC writes to this register under the following conditions:

•

The receiver runs out of descriptors.

•

The receiver was halted because an error condition was encountered while receiving a

frame.

Software must clear the QHLT bit to take the FEC’s receiver function out of a halt state.

Figure 21-24 describes the definition for the RSTAT register.

Table 21-22. RCTRL Field Descriptions

Bits

Name

Description

0–26

—

Reserved

BC_REJ

Broadcast frame reject. If this bit is set, frames with DA

(destination address) = 0xFFFF_FFFF_FFFF are rejected unless RCTRL[PROM] is set. If both

BC_REJ and PROM are set, then frames with broadcast DA are accepted and the M (MISS) bit

is set in the receive BD.

0 Broadcast frame reject is disabled.

1 Broadcast frame reject is enabled.

PROM

Promiscuous mode. When set, all frames except pause frames are accepted.

0 Promiscuous mode is disabled.

1 Promiscuous mode is enabled.

RSF

Receive short frame mode. When set, enables the reception of frames shorter than MINFLR

bytes. Note that in order for short frames to be received when RSF is set, a DA hit must occur.

When RSF is cleared, all frames shorter than MINFLR are automatically rejected.

0 Receive short frame mode is disabled.

1 Receive short frame mode is enabled.

30–31

—

Reserved

R 0

000 0000

QHLT

000 0000 0000 0000 00000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6304

Figure 21-24. RSTAT Register Definition

MPC8540 Datasheet(PDF) 1172 Page - Freescale Semiconductor, Inc

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