MPC8540 datasheet(1168/1302 Pages) FREESCALE

1168 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-28

Freescale Semiconductor

10/100 Fast Ethernet Controller

Table 21-17 describes the fields of the CTBPTR register.

21.5.3.3.5 Transmit Buffer Descriptor Pointer Register (TBPTR)

TBPTR contains the low-order 32 bits of the next transmit buffer descriptor address. Figure 21-19

describes the definition for the TBPTR register. This register takes on the value of TBASE when

the TBASE register is written by software.

Table 21-18 describes the fields of the TBPTR register.

21.5.3.3.6 Transmit Descriptor Base Address Register (TBASE)

The TBASE register is written by the user with the TxDB base address. The value must be

divisible by eight for the 8-byte data buffer descriptors. Figure 21-20 describes the definition for

the TBASE register.

Table 21-17. CTBPTR Field Descriptions

Bits

Name

Description

0–28

CTBPTR

Internally written by the DMA module. The value increments by eight (bytes) each time a descriptor

is read from memory.

29–31

—

Reserved

28 29

TBPTR

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6184

Figure 21-19. TBPTR Register Definition

Table 21-18. TBPTR Field Descriptions

Bit

Name

Description

0–28

TBPTR

Internally written by the DMA module. The value increments by eight (bytes) each time a

descriptor is read from memory.

29–31

—

Reserved

28 29

TBASE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6204

Figure 21-20. TBASE Register Definition

MPC8540 Datasheet(PDF) 1168 Page - Freescale Semiconductor, Inc

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