MPC8540 datasheet(1171/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-31

21.5.3.3.8 Out-of-Sequence Tx Data Buffer Pointer Register (OSTBDP)

The out-of-sequence Tx data buffer pointer register (OSTBDP), shown in Figure 21-22, is written

by the user and contains the data buffer pointer fields in the same format as a regular TxBD and,

together with OSTBD, provides the complete 8-byte descriptor. This area must be cleared while

not in use.

Table 21-21 describes the field of the OSTBDP register.

21.5.3.4 FEC Receive Control and Status Registers

This section describes the control and status registers that are used specifically for receiving

Ethernet frames. All of the registers are 32 bits wide.

21.5.3.4.1 Receive Control Register (RCTRL)

The RCTRL, shown in Figure 21-23, controls the operational mode of the receive block. It must

be written only after a system reset (at initialization) or if DMACTRL[GRS] is zero.

OSTBDP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_62B4

Figure 21-22. OSTBDP Register Definition

Table 21-21. OSTBDP Field Descriptions

Bita

Name

Description

0–31

OSTDBP

Out-of-sequence Tx data buffer pointer. Written by user. The Tx data buffer pointer contains the

address of the associated data buffer. There are no alignment requirements for this address.

015 16

30 31

R 0 0 000 000 000 000 0 0 0 0 0 0

0 00 0

BC_REJ PROM RSF

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6300

Figure 21-23. RCTRL Register Definition

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