MPC8540 datasheet(1169/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-29

Table 21-19 describes the fields of the TBASE register.

21.5.3.3.7 Out-of-Sequence TxBD Register (OSTBD)

The out-of-sequence TxBD register (OSTBD), shown in Figure 21-21, includes the status/control

and data length in the same format as a regular TxBD. It is useful for sending flow control frames.

The OSTBD[R] is always checked between frames. If it is not ready, a regular frame is sent. If a

flow control frame is sent and OSTBD[I] is set, a TXC event is generated after frame transmission.

This area must be cleared while not in use. Once the TSEC is in paused mode the out-of-sequence

buffer descriptor cannot be used to send another flow control frame because the MAC regards it

as a regular TxBD.

Table 21-20 describes the fields of the OSTBD register.

Table 21-19. TBASE Field Descriptions

Bits

Name

Description

0–28

TBASE

Transmit base. Defines the starting location in the memory map for the FEC TxBDs. This field must

be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how

many BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the

FEC transmit function.

29–31

—

Reserved

3 4

R PAD/CRC W I

TC DEF TO1 HFE/LC RL

OSTBDLEN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_62B0

Figure 21-21. OSTBD Register Definition

Table 21-20. OSTBD Field Descriptions

Bits

Name

Description

Ready. Written by both the FEC and the user.

0 The data buffer associated with this BD is not ready for transmission. The user is free to

manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer was

transmitted or after an error condition is encountered.

1 The data buffer, prepared for transmission by the user, was not transmitted or is currently being

transmitted. No fields of this BD may be written by the user once this bit is set.

PAD/CRC

Padding and CRC attachment for short frames. (Valid only when MACCFG2[PAD/CRC] is

cleared, and MACCFG2[CRC EN] is cleared.) If MACCFG2[PAD/CRC] is set, pads are added to

all short frames, however, this bit is ignored.

0 Do not add pads to short frames unless OSTBD[TC] is set.

1 Add pads to short frames. Pad bytes are inserted until the length of the transmitted frame

equals 64 bytes. Unlike the MPC8260 which pads up to MINFLR value, FEC always pads up

to the IEEE minimum frame length of 64 bytes.

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