MPC8540 datasheet(1167/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-27

Table 21-15 describes the fields of the TSTAT register.

21.5.3.3.3 TxBD Data Length Register (TBDLEN)

TBDLEN is a DMA register that contains the number of bytes remaining in the current transmit

buffer. Figure 21-17 describes the definition for the TBDLEN register.

Table 21-16 describes the fields of the TBDLEN register.

21.5.3.3.4 Current Transmit Buffer Descriptor Pointer Register (CTBPTR)

CTBPTR, shown in Figure 21-18, contains the address of the transmit buffer descriptor either

currently being processed, or processed most recently.

Table 21-15. TSTAT Field Descriptions

Bit

Name

Description

THLT

Transmit halt

0 No hardware initiated transmission halt.

1 FEC transmission function halted. Set by the FEC to inform the user that it is no longer

processing transmit frames and the transmit DMA function is disabled by hardware. To re-start

the transmission function, the user must clear this bit by writing a one.

1–31

—

Reserved

015 16

R 0

000

TBDLEN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_610C

Figure 21-17. TBDLEN Register Definition

Table 21-16. TBDLEN Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 TBDLEN Internally written by the DMA module. The transmit channel remains active until TBDLEN is 0.

28 29

RCTBPTR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6124

Figure 21-18. CTBPTR Register Definition

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