MPC8540 datasheet(1166/1302 Pages) FREESCALE

1166 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-26

Freescale Semiconductor

10/100 Fast Ethernet Controller

Table 21-14 describes the fields of the TCTRL register.

21.5.3.3.2 Transmit Status Register (TSTAT)

This register is written by the FEC to convey DMA status information. Figure 21-16 describes the

definition for the TSTAT register.

Table 21-14. TCTRL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

THDF

Transmit half-duplex flow control. Written by user. This bit is not self-resetting.

0 Disable back pressure.

1 Back pressure is applied to media.

21–26

—

Reserved

RFC_PAUSE Receive flow control pause frame. Written by the FEC. This read-only status bit is set if a flow

control pause frame was received and the transmitter is paused for the duration defined in

the received pause frame. This bit automatically clears after the pause duration is complete.

0 Pause duration complete.

1 Pause duration in progress.

TFC_PAUSE Transmit flow control pause frame. Use this bit to transmit a PAUSE frame. To transmit a flow

control pause frame, first set FIFO_PAUSE_CTRL[TFC_PAUSE_EN]. Next, set

MACCFG1[GTS]. If TFC_PAUSE is then set, the MAC stops transmission of data frames

after the current transmission completes. The GTSC interrupt in the IEVENT register is

asserted. With transmission of data frames stopped, the MAC transmits a MAC control

PAUSE frame with the duration value obtained from the PTV register. The TXC interrupt

occurs after sending the control pause frame. Next, the MAC clears TFC_PAUSE and

resumes transmitting data frames. Note that if the transmitter is paused due to user assertion

of GTS or reception of a PAUSE frame, the MAC may still transmit a MAC control PAUSE

frame.

0 No outstanding pause frame transmission request.

1 Pause frame transmission requested.

29–31

—

Reserved

THLT

0000000 0000000 00000000 0000000

Reset:

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6104

Figure 21-16. TSTAT Register Definition

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