MPC8540 datasheet(1162/1302 Pages) FREESCALE

1162 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-22

Freescale Semiconductor

10/100 Fast Ethernet Controller

avoid an underrun condition. Underrun is an error condition in which data is not retrieved from

external memory quickly enough, leaving the TX FIFO empty before the complete frame is

transmitted. Because different combinations of events, several of which are determined by the

user, can lead to underrun, the FEC provides several FIFO registers that allow the user to select

the proper setting to be able to tune the system and obtain the maximum performance with minimal

chance of underrun. The principal causes for underrun in the FEC are:

•

Misaligned data buffer addresses

•

Small data buffer sizes

•

Combinations of the above

It is recommended that the minimum size data buffers be 64 bytes and that data buffers be 64-byte

aligned. The user can deviate from these recommended values to try to increase performance or to

use less memory, but unless the default values of some of the FIFO registers are adjusted, the

probability of an underrun may also increase. The FIFO_TX_THR (default is 512 entries)

indicates the amount of data required to be in the FIFO before starting the transmission of a frame.

The FIFO_TX_STARVE (default is 128 entries) is used to indicate that the amount of data in the

FIFO is so low that the risk of underrun is extremely high. The FIFO_TX_STARVE_SHUTOFF

(default is 512 entries) contains the watermark level to be used for exiting the starve state. These

registers are intended to allow the user to make the proper trade-off. If triggered, the starve mode,

for instance, automatically raises the priority of FEC fetches from memory.

21.5.3.2.1 FIFO Pause Control Register (FIFO_PAUSE_CTRL)

FIFO_PAUSE_CTRL, shown in Figure 21-11, is writable by the user to configure the properties

of the FEC FIFO.

Table 21-10 describes the fields of the FIFO_PAUSE_CTRL register.

000

Reset

0000_0000_0000_0000

000

TFC_PAUSE_EN

Reset

0000_0000_0000_0000

Offset

0x2_604C

Figure 21-11. FIFO_PAUSE_CTRL Register Definition

MPC8540 Datasheet(PDF) 1162 Page - Freescale Semiconductor, Inc