MPC8540 datasheet(1159/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-19

Table 21-7 describes the fields of the MINFLR register.

21.5.3.1.5 Pause Time Value Register (PTV)

PTV, shown in Figure 21-9, is written by the user to store the pause duration used when the FEC

initiates a pause frame through TCTRL[TFC_PAUSE]. The low-order 16 bits (PT) represent the

pause time and the high-order 16 bits (PTE) represent the extended pause control parameter. The

pause time is measured in units of pause_quanta, equal to 512 bit times. The pause time can range

from 0 to 65,535 pause_quanta, or 0 to 33,553,920 bit times. See Section 21.6.2.6, “Flow

Control,” for additional details.

Table 21-7. MINFLR Field Descriptions

Bits

Name

Description

0–24

—

Reserved

25–31 MINFLR Minimum receive frame length (typically 64 decimal, which is the maximum). Ethernet discards

incoming frames shorter than MINFLR unless RCTRL[RSF] (receive short frames) is set, in which

case RxBD[SH] (frame too short) is set in the last RxBD. Unlike the MPC8260, in which pads are

added to make the transmit frame equal to MINFLR bytes, if padding is requested, the FEC always

pads transmit frames to 64 bytes ignoring MINFLR. MINFLR is only used to determine the minimum

size of acceptable receive frames.

015 16

PTE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6028

Figure 21-9. PTV Register Definition

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