MPC8540 datasheet(1155/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-15

EBERR Ethernet bus error. This bit indicates that a system bus error occurred while a DMA transaction was

underway. If the EBERR is set while transmission is in progress, the DMA stops sending data to the

Tx FIFO which eventually causes an underrun error (XFUN) and TSTAT[THLT] is set. If the EBERR is

set while receiving a frame, the DMA discards the frame and RSTAT[QHLT] is set.

0 No system bus error occurred.

1 System bus error occurred.

4—

Reserved

MSRO

MSTAT register overflow. This interrupt is asserted if the count for one of the MSTAT registers has

exceeded the size of the register.

0 MSTAT count not exceeding register size.

1 MSTAT count exceeds register size.

GTSC

Graceful transmit stop complete. This interrupt is asserted following the completion of a graceful stop,

which was intitiated by setting either DMACTRL[GTS] or TCTRL[TFC_PAUSE]. Graceful stop means

that the transmitter is put into a pause state after completion of the frame currently being transmitted.

0 No graceful stop interrupt.

1 Graceful stop requested.

BABT

Babbling transmit error. This bit indicates that the transmitted frame length has exceeded the value in

the MAC’s Maximum Frame Length register and MACCFG2[Huge Frame] is cleared. Frame truncation

occurs when this condition occurs. TxBD[TXTRUNC] is set in the last TxBD (TxBD[L] is set) of the

frame.

0 Transmitted frame length not exceeding maximum frame length.

1 Transmitted frame length exceeding maximum frame length.

TXC

Transmit control interrupt. This bit indicates that a control frame was transmitted.

0 Control frame not transmitted.

1 Control frame transmitted.

TXE

Transmit error. Indicates that an error occurred on the transmitted channel that caused TSTAT[THLT]

to be set by the FEC. This bit is set whenever any transmit error occurs that causes the transmitter to

halt (EBERR, LC, CRL/XDA, XFUN). It is not set if DMACTRL[WOP] is set and the FEC runs out of

TxBDs to process. In order to begin transmitting packets again, the user must clear TSTAT[THLT].

0 No transmit channel error occurred.

1 Transmit channel error occurred.

TXB

Transmit buffer. Indicates that a transmit buffer descriptor was updated whose I (Interrupt) bit was set

in its status word and was not the last buffer descriptor of the frame.

0 No transmit buffer descriptor updated.

1 Transmit buffer descriptor updated.

TXF

Transmit frame interrupt. Indicates that a frame was transmitted and that the last corresponding

transmit buffer descriptor (TxBD) was updated. This only occurs if the I (Interrupt) bit in the status word

of the buffer descriptor is set.

0 No frame transmitted/TxBD not updated.

1 Frame transmitted/TxBD updated.

—

Reserved

Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in

half-duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.

0 No late collision occurred.

1 Late collision occurred.

Table 21-4. IEVENT Field Descriptions (continued)

Bits

Name

Description

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