MPC8540 datasheet(1153/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-13

21.5.3 Memory-Mapped Register Descriptions

This section provides a detailed description of the FEC registers. Because all of these registers are

32 bits wide, only 32-bit register accesses are supported.

21.5.3.1 FEC General Control and Status Registers

This section describes general control and status registers used for both transmitting and receiving

Ethernet frames. All of the registers are 32 bits wide.

21.5.3.1.1 Interrupt Event Register (IEVENT)

If an event occurs that sets a bit in the interrupt event (IEVENT) register, shown in Figure 21-5,

an interrupt is generated if the corresponding bit in the interrupt enable register (IMASK) is also

set. The bit in the interrupt event register is cleared if a 1 is written to that bit position. A write of

0 has no effect.

0x2_6880

GADDR0—Group address register 0

R/W

0x0000_0000

21.5.3.7.2/21-46

0x2_6884

GADDR1—Group address register 1

R/W

0x0000_0000

0x2_6888

GADDR2—Group address register 2

R/W

0x0000_0000

0x2_688C

GADDR3—Group address register 3

R/W

0x0000_0000

0x2_6890

GADDR4—Group address register 4

R/W

0x0000_0000

0x2_6894

GADDR5—Group address register 5

R/W

0x0000_0000

0x2_6898

GADDR6—Group address register 6

R/W

0x0000_0000

0x2_689C

GADDR7—Group address register 7

R/W

0x0000_0000

0x2_68A0–

0x2_6AFF

Reserved

0x0000_0000

—

FEC Attribute Registers

0x2_6B00–

0x2_6BF4

Reserved

0x0000_0000

—

0x2_6BF8

ATTR—Attribute register

R/W

0x0000_0000

21.5.3.8.1/21-46

0x2_6BFC

ATTRELI—Attribute EL & EI register

R/W

0x0000_0000

21.5.3.8.2/21-47

FEC Future Expansion Space

0x2_6C00–

0x2_6FFF

Reserved

0x0000_0000

—

1 R = Read Only, W = Write Only, R/W = Read and Write, LH = Latches High, SC = Self-clearing.

Table 21-3. Module Memory Map (continued)

Offset

Name

Access 1

Reset

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