MPC8540 datasheet(1150/1302 Pages) FREESCALE

1150 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-10

Freescale Semiconductor

10/100 Fast Ethernet Controller

Table 21-2 defines the top-level memory map.

21.5.2 Detailed Memory Map

Table 21-3 shows the address of each register, the name of the register, and a cross-reference to the

complete description of the register.

Table 21-2. Module Memory Map Summary

Address

Function

000–0FF

FEC general control/status registers

100–2FF

FEC transmit control/status registers

300–4FF

FEC receive control/status registers

500–5FF

FEC MAC registers

600–7FF

Reserved

800–8FF

FEC HASH function registers

900–AFF

Reserved

B00–BFF

FEC attribute registers

C00–FFF

Future expansion space

Table 21-3. Module Memory Map

Offset

Name

Access 1

Reset

Section/Page

FEC General Control and Status Registers

0x2_6000–

0x2_600C

Reserved

0x0000_0000

—

0x2_6010

IEVENT—Interrupt event register

0x0000_0000

21.5.3.1.1/21-13

0x2_6014

IMASK—Interrupt mask register

R/W

0x0000_0000

21.5.3.1.2/21-16

0x2_6018

EDIS—Error disabled register

R/W

0x0000_0000

21.5.3.1.3/21-18

0x2_601C–

0x2_6020

Reserved

0x0000_0000

—

0x2_6024

MINFLR—Minimum frame length register

R/W

0x0000_0040

21.5.3.1.4/21-18

0x2_6028

PTV—Pause time value register

R/W

0x0000_0000

21.5.3.1.5/21-19

0x2_602C

DMACTRL—DMA control register

R/W

0x0000_0000

21.5.3.1.6/21-20

0x2_6030–

0x2_6088

Reserved

0x0000_0000

—

FEC FIFO Control and Status Registers

0x2_604C

FIFO_PAUSE_CTRL—FIFO pause control register

R/W

0x0000_0000

21.5.3.2.1/21-22

0x2_608C

FIFO_TX_THR—FIFO transmit threshold register

R/W

0x0000_0080

21.5.3.2.2/21-23

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