MPC8540 datasheet(1146/1302 Pages) FREESCALE

1146 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-6

Freescale Semiconductor

10/100 Fast Ethernet Controller

The most-significant byte of data in a receive or transmit data buffer corresponds to the

most-significant byte of a frame, respectively.

The complete FEC is designed for single MAC applications. The FEC supports the 10/100 Mbps

MII interface to connect to an external Ethernet transceiver.

The FEC software programming model is similar to the MPC8260 (PowerQUICC II) device.

Hence, it enables Freescale Semiconductor customers to leverage already implemented Ethernet

drivers, reducing the software development cycle.

21.2 Features

The MPC8540 FEC includes these distinctive features:

•

IEEE 802.3, 802.3u, 802.3x, 802.3ac compliant

•

Support for different Ethernet physical interfaces:

— 10/100 Mbps IEEE 802.3 MII

— 10 Mbps IEEE 802.3 MII

•

Full- and half-duplex support

•

IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software

programmed PAUSE frame generation and recognition)

•

Support for out-of-sequence transmit queue (for initiating flow control)

•

Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and

IEEE 802.1 virtual local area network (VLAN) frames

•

Retransmission from transmit FIFO following a collision

•

Support for CRC generation and verification of inbound/outbound packets

•

Address recognition

— Each exact match can be programmed to be accepted or rejected

— Broadcast address (accept/reject)

— Exact match 48-bit individual (unicast) address

— Hash (256-bit hash) check of individual (unicast) addresses

— Hash (256-bit hash) check of group (multicast) addresses

— Promiscuous mode

•

Extraction data and its associated buffer descriptors can be directed to processor’s L2 cache

to reduce access latency

MPC8540 Datasheet(PDF) 1146 Page - Freescale Semiconductor, Inc

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