MPC8540 datasheet(1149/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-9

21.5 Memory Map/Register Definition

The FEC uses a software model similar to that employed by the Fast Ethernet function supported

on the Freescale Semiconductor MPC8260 CPM FCC and in the 10/100 controller of the

MPC860T.

The FEC is programmed by a combination of control/status registers (CSRs) and buffer

descriptors. The CSRs are used for mode control, interrupts, and to access status information. The

descriptors are used to pass data buffers and related buffer status or frame information between the

hardware and software.

All accesses to and from the registers must be made with 32-bit accesses. There is no support for

accesses of sizes other than 32 bits.

This section of the document defines the memory map and describes the registers in detail. The

buffer descriptors are described in Section 21.6.3, “Buffer Descriptors.”

The MII registers are described in this section.

21.5.1 Top-Level Module Memory Map

The FEC implementation requires 4 Kbytes of memory-mapped space, of which more than

1 Kbyte is reserved for future expansion. The space is divided into the following sections:

•

General control/status registers

•

Transmit-specific control/status registers

•

Receive specific control/status registers

•

MAC registers

•

Hash function registers

FEC_TX_ER

Transmit error

State

Meaning

Asserted/Negated—Assertion of this signal for one or more clock cycles while

FEC_TX_EN is asserted causes the PHY to transmit one or more illegal symbols.

Asserting FEC_TX_ER has no effect when operating at 10 Mbps or when

FEC_TX_EN is negated.

Timing Asserted/Negated—This signal transitions synchronously with respect to

FEC_TX_CLK.

Table 21-1. FEC Signals—Detailed Signal Descriptions (continued)

Signal

I/O

Description

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