MPC8540 datasheet(1148/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-8

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.4.1 Detailed Signal Descriptions

Table 21-1 provides a detailed description of the FEC interface signals. The modes follow the

IEEE 802.3 standard, 2000 Edition. Input signals not used are internally disabled. Output signals

not used are driven low.

Table 21-1. FEC Signals—Detailed Signal Descriptions

Signal

I/O

Description

FEC_COL

Collision. The behavior of this signal is not specified when in full-duplex mode.

State

Meaning

Asserted/Negated—Asserted upon detection of a collision. It must remain asserted

while the collision persists.

Timing Asserted/Negated—Not required to transition synchronously with FEC_TX_CLK or

FEC_RX_CLK.

FEC_CRS

Carrier sense. Used as SDET (signal detect), an optional signal that some PHYs generate.

State

Meaning

Asserted/Negated—Asserted when the transmit or receive medium is not idle. In case

of a collision, FEC_CRS must stay asserted through the duration of the collision.

Timing Asserted/Negated—Not required to transition synchronously with FEC_TX_CLK or

FEC_RX_CLK.

FEC_RX_CLK

Receive clock. This is a continuous clock (2.5, or 25 MHz) that provides a timing reference for

FEC_RX_DV, FEC_RXD, and FEC_RX_ER.

FEC_RX_DV

Receive data valid. If FEC_RX_DV is asserted, the PHY is indicating that valid data is present on

the MII interfaces.

FEC_RXD[3:0

]

Receive data in. Represents a nibble of data to be transferred from the PHY to the MAC when

FEC_RX_DV is asserted. A completely formed SFD must be passed across the MII. When

FEC_RX_DV is not asserted, FEC_RXD has no meaning.

FEC_RX_ER

Receive error

State

Meaning

Asserted—When FEC_RX_ER and FEC_RX_DV are asserted, the PHY has detected

an error in the current frame.

Negated—The PHY has not detected an error in the current frame.

FEC_TX_CLK

Transmit clock in. FEC_TX_CLK is a continuous clock (with a frequency of 2.5 or 25 MHz) that

provides a timing reference for FEC_TX_EN, FEC_TXD, and FEC_TX_ER. FEC_TX_CLK is

generated in the PHY and provided to the MAC.

FEC_TXD[3:0]

Transmit data out

State

Meaning

Asserted/Negated—Represents a nibble of data to be sent from the MAC to the PHY

when FEC_TX_EN is asserted; has no meaning if FEC_TX_EN is negated.

FEC_TX_EN

Transmit data valid

State

Meaning

Asserted—The MAC is indicating that valid data is present on the MII.

Negated—Valid data is not guaranteed to be present on the MII.

Timing Asserted/Negated—This signal transitions synchronously with respect to

FEC_TX_CLK.

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