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MPC8540 Datasheet(PDF) 1145 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1145 Page - Freescale Semiconductor, Inc

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Introduction
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
21-5
The LLC defines service access for protocols that conform to the open system interconnection
(OSI) model for network protocols. However, many protocols do not obey the rules for those
layers and additional information must be added to the LLC in order to provide information
regarding those protocols. Protocols that fall into this category include IP and IPX. The method
used to provide this additional protocol information is called a subnetwork access protocol
(SNAP) frame. A SNAP encapsulation is indicated by the DSAP and SSAP addresses being set to
0xAA and the LLC control field being set to 0x03. If that address is seen, a SNAP header follows.
The SNAP header is five bytes long. The first three bytes consist of the organization code (SNAP
OUI), which is assigned by the IEEE. The last two bytes become the type value set from the
original Ethernet specifications if SNAP OUI = 0, or they become a SNAP protocol identifier if
SNAP OUI is nonzero.
The FEC allows the flexibility to accelerate the identification and retrieval of all the standard and
non-standard protocols mentioned above. Figure 21-4 depicts the block diagram of the FEC.
Figure 21-4. FEC Block Diagram
21.1.1 10/100 Fast Ethernet Controller Overview
The FEC is designed to support 10/100 Mbps Ethernet/802.3 networks and contains the following
components:
•
Ethernet media access controller (MAC)
•
First-in first-out (FIFO) controller
•
Direct memory access (DMA) controller
Address/Data
filtering
MAC Layer
DMA
Tx system CLK
data path
Pack
words
Unpack
words
Rx FIFO
1 kbyte
FIFO
control
Tx FIFO
1 kbyte
Tx/Rx descriptors
Tx/Rx data
Tx/Rx status
Block
interface
Clocks
MII Mgmt
To PHY



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