MPC8540 datasheet(1147/1302 Pages) FREESCALE

1147 / 1302 page

Modes of Operation

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-7

21.3 Modes of Operation

The FEC’s primary operational modes are the following:

•

Full- and half-duplex operation. Determined by MACCFG2 Full_Duplex bit. Full-duplex

mode is intended for use on point to point links between switches or end node to switch.

Half-duplex mode is used in connections between an end node and a repeater or between

repeaters.

If configured in half-duplex mode (only 10 and 100 Mbps operation, MACCFG2 register’s

Full_Duplex bit is cleared), the MAC complies with the IEEE CSMA/CD access method.

If configured in full-duplex mode (10/100 Mbps operation; MACCFG2 register’s

Full_Duplex bit is set), the MAC supports flow control. If flow control is enabled, it allows

the MAC to receive or send PAUSE frames.

•

10 Mbps and 100 Mbps MII interface operation. The MAC-PHY interface operates in MII

mode by configuring bits 22–23 of MACCFG2 (MACCFG2[I/F_Mode] = 01). The MII is

the media-independent interface defined by the 802.3 standard for 10/100 Mbps operation.

Operation speed is determined by the FEC_TX_CLK and FEC_RX_CLK signals which are

driven by the transceiver. The transceiver auto negotiates the speed.

•

Address recognition options

The options supported are promiscuous, broadcast, exact individual address hash or exact

match, and multicast hash match. For detailed descriptions refer to Section 21.5.3.7.1,

“Individual Address Registers 0–7 (IADDRn),” Section 21.5.3.7.2, “Group Address

Registers 0–7 (GADDRn),” Section 21.5.3.4.1, “Receive Control Register (RCTRL),” and

Section 21.6.2.5, “Frame Recognition.”

•

Internal loop back

Internal loop back mode is selected via the Loop_Back bit in the MACCFG1 register. See

Section 21.6.2.9, “Internal and External Loop Back,” for details.

21.4 External Signal Descriptions

This section defines the FEC-to-chip signals. The buses are described using the bus convention

used in IEEE 802.3 because the PHY follows this same convention (that is, TxD[3:0] means 0 is

the lsb). Notice that except for external physical interfaces the buses and registers follow a

big-endian format.

The FEC network interface supports the MII option that requires 15 I/O signals. The MII option

supports both 10- and 100-Mbps Ethernet rates.

MPC8540 Datasheet(PDF) 1147 Page - Freescale Semiconductor, Inc