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MPC8540 Datasheet(PDF) 1151 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1151 Page - Freescale Semiconductor, Inc |
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1151 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 21-11 0x2_6090– 0x2_6094 Reserved R 0x0000_0000 — 0x2_6098 FIFO_TX_STARVE—FIFO transmit starve register R/W 0x0000_0020 21.5.3.3.4/21-27 0x2_609C FIFO_TX_STARVE_SHUTOFF—FIFO transmit starve shutoff register R/W 0x0000_0080 21.5.3.3.5/21-28 0x2_60A0– 0x2_60FC Reserved R 0x0000_0000 — FEC Transmit Control and Status Registers 0x2_6100 TCTRL—Transmit control register R/W 0x0000_0000 21.5.3.3.1/21-25 0x2_6104 TSTAT—Transmit status register R/W 0x0000_0000 21.5.3.3.2/21-26 0x2_6108 Reserved R 0x0000_0000 — 0x2_610C TBDLEN—TxBD data length R 0x0000_0000 21.5.3.3.3/21-27 0x2_6110– 0x2_6120 Reserved R 0x0000_0000 — 0x2_6124 CTBPTR—Current TxBD pointer register R 0x0000_0000 21.5.3.3.4/21-27 0x2_6128– 0x2_6180 Reserved R 0x0000_0000 — 0x2_6184 TBPTR—TxBD pointer register R/W 0x0000_0000 21.5.3.3.5/21-28 0x2_6188– 0x2_6200 Reserved R 0x0000_0000 — 0x2_6204 TBASE—TxBD base address register R/W 0x0000_0000 21.5.3.3.6/21-28 0x2_6208– 0x2_62AC Reserved R 0x0000_0000 — 0x2_62B0 OSTBD—Out-of-sequence TxBD register R/W 0x0000_0000 21.5.3.3.7/21-29 0x2_62B4 OSTBDP—Out-of-sequence TxBD pointer register R/W 0x0000_0000 21.5.3.3.8/21-31 0x2_62B8– 0x2_62FC Reserved R 0x0000_0000 — FEC Receive Control and Status Registers 0x2_6300 RCTRL—Receive control register R/W 0x0000_0000 21.5.3.4.1/21-31 0x2_6304 RSTAT—Receive status register R/W 0x0000_0000 21.5.3.4.2/21-32 0x2_6308 Reserved R 0x0000_0000 — 0x2_630C RBDLEN—RxBD data length register R 0x0000_0000 21.5.3.4.3/21-33 0x2_6310– 0x2_6320 Reserved R 0x0000_0000 — 0x2_6324 CRBPTR—Current RxBD pointer register R 0x0000_0000 21.5.3.4.4/21-33 Table 21-3. Module Memory Map (continued) Offset Name Access 1 Reset Section/Page |
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