MPC8540 datasheet(1154/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-14

Freescale Semiconductor

10/100 Fast Ethernet Controller

These interrupts can be divided into operational interrupts, transceiver/network error interrupts,

and internal error interrupts. Interrupts that may occur in normal operation are:

•

GTSC, GRSC, TXF, TXB, TXC, RXF, RXB, RXC, and MSRO

Interrupts resulting from errors/problems detected in the network or transceiver are:

•

BABR, BABT, LC, and CRL/XDA

Interrupts resulting from internal errors are:

•

EBERR, XFUN, and BSY

Table 21-4 describes the fields of the IEVENT register.

678

BABR RXC

BSY EBERR

MSRO GTSC BABT

TXC

TXE

TXB

TXF

CRL/

XDA

XFUN

Reset

0000_0000_0000_0000

RXB

GRSC RXF

Reset

0000_0000_0000_0000

Offset

0x2_6010

Figure 21-5. IEVENT Register Definition

Table 21-4. IEVENT Field Descriptions

Bits

Name

Description

BABR

Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s

maximum frame length register while MACCFG2[Huge Frame] is set.

0 Excessive frame not received

1 Excessive frame received

RXC

Receive control interrupt. A control frame was received. If MACCFG1[Rx_Flow] is set, a pause

operation is performed lasting for the duration specified in the received pause control frame and

beginning when the frame was received.

0 Control frame not received

1 Control frame received

BSY

Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.

When IEVENT[BSY] is set RSTAT[QHLT] is also set. In order to begin receiving packets again, the user

must clear RSTAT[QHLT]. This bit and RSTAT[QHLT] are set whenever the FEC reads an RxBD with

its Empty field cleared.

0 No frame received and discarded.

1 Frame received and discarded.

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