MPC8540 datasheet(1156/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-16

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.5.3.1.2 Interrupt Mask Register (IMASK)

The interrupt mask register, shown in Figure 21-6, provides control over which possible interrupt

events are allowed to generate an actual interrupt. All implemented bits in this CSR are R/W. This

IMASK registers are set, an interrupt is generated. The interrupt signal can be cleared by clearing

the corresponding IEVENT bit.

CRL/

XDA

Collision retry limit/excessive defer abort. Indicates either one of two conditions occurred while

attempting to transmit a frame: 1) the number of successive transmission collisions has exceeded the

MAC’s HAFDUP[Retransmission Maximum] count or 2) an excessive defer abort condition has

occurred. An excessive defer abort condition occurs when the TSEC waits more than 3036 bytes while

attempting to send a frame and HAFDUP[EXCESS_DEFER] is 0. The TxBD[DEF] or OSTBD[DEF] is

also set. In either case the frame is discarded without being transmitted and the TSEC is halted

(TSTAT[THLT] is set). The CRL or XDA condition can only occur while in half-duplex mode.

0 Successive transmission collisions do not exceed maximum and no excessive defer abort condition

has occurred.

1 Successive transmission collisions exceed maximum or an excessive defer abort condition has

occurred.

XFUN

Transmit FIFO underrun. Indicates that the transmit FIFO became empty before the complete frame

was transmitted.

0 Transmit FIFO not underrun.

1 Transmit FIFO underrun.

RXB

Receive buffer. Indicates that a receive buffer descriptor was updated which had the I (Interrupt) bit set

in its status word and was not the last buffer descriptor of the frame.

0 Receive buffer descriptor not updated.

1 Receiver buffer descriptor updated.

17–22

—

Reserved

GRSC

Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It

allows the user to know if the system has completed the stop and it is safe to write to receive registers

(status, control or configuration registers) that are used by the system during normal operation.

0 Graceful stop not completed.

1 Graceful stop completed.

RXF

Receive frame interrupt. The last receive buffer descriptor (RxBD) of a frame was updated. This occurs

only if the I (interrupt) bit in the buffer descriptor status word is set.

0 Frame not received.

1 Frame received.

25–31

—

Reserved

Table 21-4. IEVENT Field Descriptions (continued)

Bits

Name

Description

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