MPC8540 datasheet(1160/1302 Pages) FREESCALE

1160 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-20

Freescale Semiconductor

10/100 Fast Ethernet Controller

Table 21-8 describes the fields of the PTV register.

21.5.3.1.6 DMA Control Register (DMACTRL)

DMACTRL is writable by the user to configure the DMA block. Figure 21-10 describes the

definition for the DMACTRL register.

Table 21-9 describes the fields of the DMACTRL register.

Table 21-8. PTV Field Descriptions

Bits

Name

Description

0–15

PTE

Extended pause control. This field allows software to add a 16-bit additional control parameter into the

pause frame to be sent when TCTRL[TFC_PAUSE] is set. Note that current IEEE 802.3 pause frame

format requires this parameter to be set to 0.

16–31

Pause time value. Represents the 16-bit pause quanta (that is, 512 bit times). This pause value is used

as part of the pause frame to be sent when TCTRL[TFC_PAUSE] is set. See Section 21.6.2.6, “Flow

Control,” for more information.

023

R0 0000000000000 000000000 0

TDSEN TBDSEN

GRS GTS

WWR WOP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_602C

Figure 21-10. DMACTRL Register Definition

Table 21-9. DMACTRL Field Descriptions

Bits

Name

Description

0–23

—

Reserved

TDSEN

Tx data snoop enable

0 Disables snooping of all transmit frames from memory.

1 Enables snooping of all transmit frames from memory.

TBDSEN

TxBD snoop enable

0 Disables snooping of all transmit BD memory accesses.

1 Enables snooping of all transmit BD memory accesses.

—

Reserved

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