MPC8540 datasheet(1161/1302 Pages) FREESCALE

1161 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-21

21.5.3.2 FEC FIFO Control and Status Registers

The following registers allow the user to change some of the default settings in the FIFO that can

be used to optimize operation for performance or for safety. They must be set carefully in order to

GRS

Graceful receive stop. If this bit is set, the Ethernet controller stops receiving frames following

completion of the frame currently being received. (That is, after a valid end of frame was received).

The buffer of the receive frame associated with the EOF is closed and the IEVENT[GRSC] is set.

Because the MAC’s receive enable bit (MACCFG[Rx_EN]) may still be set, the MAC may continue to

receive but the FEC ignores the receive data until GRS is cleared. If this bit is cleared, the FEC scans

the input data stream for the start of a new frame (preamble sequence and start of frame delimiter)

and the first valid frame received uses the next RxBD.

If GRS is set, the user must monitor the graceful receive stop complete (GRSC) bit in the IEVENT

IEVENT[GRSC] and can write to receive registers that are accessible to both user and the FEC

hardware without fear of conflict.

0 The FEC scans the input data stream for valid frames.

1 The FEC stops receiving frames following completion of current frame.

GTS

Graceful transmit stop. If this bit is set, the Ethernet controller stops transmission after the completion

of any frame that is currently being transmitted and the GTSC interrupt in the IEVENT register is

asserted. If frame transmission is not currently underway, the GTSC interrupt is asserted immediately.

Once transmission has completed, a ‘restart’ can be accomplished by clearing GTS.

0 The FEC continues.

1 The FEC stops transmission after completion of current frame.

—

Reserved

WWR

Write with response. This bit gives the user the assurance that a BD was updated in memory before

it receives an interrupt concerning a transmit or receive frame.

0 Do not wait for acknowledgement from system for BD writes before setting IEVENT bits.

1 Before setting IEVENT bits TXB, TXF, TXE, IE, XFUN, LC, CRL/XDA, RXB, RXF, the FEC waits

for system acknowledgement that the transmit or receive BD being updated was stored in memory.

WOP

Wait or poll. This bit, which is applicable only to the transmitter, provides the user the option for the

FEC to periodically poll TxBD or to wait for software to tell FEC to fetch a buffer descriptor. While

operating in the wait mode, the FEC allows two additional reads of a descriptor which is not ready

before entering a halt state. No interrupt is driven (IEVENT[TXE] is clear). To resume transmission,

software must clear TSTAT[THLT].

Note that if this bit is set, the user must ensure that all TxBDs involved with sending a frame have their

ready bits set before any transmission begins. Otherwise, FEC behavior is boundedly undefined.

In wait mode (DMACTRL[WOP] is set) when FEC is processing a frame and an intermediate TxBD’s

ready bit is cleared, FEC does not halt, but instead continuously polls the same TxBD until the TxBD

becomes ready or an Ethernet interface error or a memory error is encountered. If the TxBD becomes

ready (TxBD[Ready] is set), FEC continues to process the frame. If an error occurs before the TxBD

becomes ready, FEC reports the error in both the IEVENT register as well as the TxBD for Ethernet

interface errors, or the IEVENT[EBERR] for a memory error and sets TSTAT[THLT].

Note: Software must eventually set all of its TxBDs for a frame, because FEC continuously reads an

intermediate TxBD until it becomes ready if insufficient data has been read to surpass the FIFO

transmit threshold (FIFO_TX_THR) register value.

0 Poll TxBD every 512 clocks.

1 Do not poll, but wait for a write to TSTAT[THLT].

Table 21-9. DMACTRL Field Descriptions (continued)

Bits

Name

Description

MPC8540 Datasheet(PDF) 1161 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1161 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL