MPC8540 datasheet(1158/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-18

Freescale Semiconductor

10/100 Fast Ethernet Controller

21.5.3.1.3 Error Disabled Register (EDIS)

The error disabled register allows the user to control the reporting of errors by the FEC. The

IEVENT bit corresponding to an error is not set if the error is disabled in the EDIS register.

Figure 21-7 shows the EDIS register.

Table 21-6 describes the fields of the EDIS register.

21.5.3.1.4 Minimum Frame Length Register (MINFLR)

MINFLR, shown in Figure 21-8, is written by the user and tells the FEC the smallest packet to

accept and place in a receive buffer pointed to by the RxBD.

BSYDIS

EBERRDIS

LCDIS

Reset

0000_0000_0000_0000

Reset

0000_0000_0000_0000

Offset

0x2_6018

Figure 21-7. EDIS Register Definition

Table 21-6. EDIS Field Descriptions

Bits

Name

Description

0–1

—

Reserved

BSYDIS

Busy disabled

EBERRDIS

Ethernet controller bus error disabled

4–12

—

Reserved

LCDIS

Late collision disabled

14–31

—

Reserved

24 25

R 0000000

0000000

00000000

000

MINFLR

Reset

0000_0000_0000_0000_0000_0000_0100_0000

Offset

0x2_6024

Figure 21-8. MINFLR Register Definition

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