MPC8540 datasheet(1163/1302 Pages) FREESCALE

1163 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-23

21.5.3.2.2 FIFO Transmit Threshold Register (FIFO_TX_THR)

The purpose of the threshold register is to trigger the unloading of FIFO data to the PHY. It

represents the numerical SRAM entry (0-255 for a 1-Kbyte FIFO) to trigger the threshold function.

If the used entry count is equal to or greater than the threshold register, then transmission can

begin. This register is read/write by software. This register is initialized to

0000_0000_0000_0000_0000_0000_1000_0000 at system reset. Figure 21-12 describes the

definition for the FIFO_TX_THR register.

Table 21-10. FIFO_PAUSE_CTRL Field Descriptions

Bits

Name

Description

0–29

—

Reserved.

TFC_PAUSE_EN

TFC_PAUSE enable. This bit enables the ability to transmit a pause control frame by setting the

TCTRL[TFC_PAUSE] bit. This bit is cleared at reset.

0 Pause control frame transmission disabled.

1 Pause control frame transmission enabled.

—

Reserved.

015 16

23 24

R 0

000

FIFO_TX_THR

Reset

0000_0000_0000_0000_0000_0000_1000_0000

Offset

0x2_608C

Figure 21-12. FIFO_TX_THR Register Definition

MPC8540 Datasheet(PDF) 1163 Page - Freescale Semiconductor, Inc