MPC8540 datasheet(1165/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-25

ends. This register is read/write by software. Figure 21-14 describes the definition for the

FIFO_TX_STARVE_SHUTOFF register.

Table 21-13 describes the fields of the FIFO_TX_STARVE_SHUTOFF register.

21.5.3.3 FEC Transmit Control and Status Registers

This section describes the control and status registers that are used specifically for transmitting

Ethernet frames. All of the registers are 32 bits wide.

21.5.3.3.1 Transmit Control Register (TCTRL)

This register is writable by the user to configure the transmit block. Figure 21-15 describes the

definition for the TCTRL register.

R 0 0 0 0 0 0 000 00 000 00 00 000 00

FIFO_TX_STARVE_SHUTOFF

Reset

0000_0000_0000_0000_0000_0000_1000_0000

Offset

0x2_609C

Figure 21-14. FIFO_TX_STARVE_SHUTOFF Register Definition

Table 21-13. FIFO_TX_STARVE_SHUTOFF Field Descriptions

Bits

Name

Description

0–23

—

Reserved

24–31

FIFO_TX_STARVE_SHUTOFF

FIFO transmit starve shutoff. Indicates the value to use to turn off the

starve state. The starve state turns off when the FIFO Rx used entry count

becomes greater than or equal to the FIFO Rx starve shutoff register.

192021

R 0 000 000 000 000 00 0 0 0 0 0

THDF

0 0 0 0 0 0 RFC_PAUSE

TFC_PAUSE

00 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6100

Figure 21-15. TCTRL Register Definition

MPC8540 Datasheet(PDF) 1165 Page - Freescale Semiconductor, Inc

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