MPC8540 datasheet(1173/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-33

Table 21-23 describes the fields of the RSTAT register.

21.5.3.4.3 RxBD Data Length Register (RBDLEN)

RBDLEN is a DMA register that contains the number of bytes remaining in the current receiver

buffer. Figure 21-25 describes the definition for the RBDLEN register.

Table 21-24 describes the fields of the RBDLEN register.

21.5.3.4.4 Current Receive Buffer Descriptor Pointer Register (CRBPTR)

CRBPTR, shown in Figure 21-26, contains the address of the receive buffer descriptor either

currently being processed, or processed most recently.

Table 21-23. RSTAT Field Descriptions

Bits

Name

Description

0–7

—

Reserved

QHLT

RxBD queue is halted. When IEVENT[BSY] or IEVENT[EBERR] is set during reception of a packet,

RSTAT[QHLT] is also set. In order to begin receiving packets again, the user must clear RSTAT[QHLT].

This bit is set whenever the FEC reads an RxBD with its Empty field cleared or encounters a system

bus error while processing an RX packet. It is a hardware-initiated stop indication (DMA_CTRL[GRS]

being set by the user does not cause this bit to be set). The current frame and all other frames directed

to the halted queue are discarded. A write with a value of 1 re-enables the queue for receiving.

0 RxBD queue is enabled for Ethernet reception. (That is, it is not halted.)

1 All Ethernet controller receive activity to RxBD queue is halted.

9–31

—

Reserved

015 16

R 0

000

RBDLEN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_630C

Figure 21-25. RBDLEN Register Definition

Table 21-24. RBDLEN Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RBDLEN The RBDLEN is internally written by the DMA module. If RBDLEN is cleared, all activity in the

receive channel stops.

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