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MPC8540 Datasheet(PDF) 1174 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1174 Page - Freescale Semiconductor, Inc |
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1174 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 21-34 Freescale Semiconductor 10/100 Fast Ethernet Controller Table 21-25 describes the fields of the CRBPTR register. \ 21.5.3.4.5 Maximum Receive Buffer Length Register (MRBLR) The MRBLR, shown in Figure 21-27, is written by the user. It informs the FEC how much space is in the receive buffer pointed to by the RxBD. Table 21-26 describes the fields of the MRBLR register. \ 0 28 29 31 R CRBPTR 0 0 0 W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x2_6324 Figure 21-26. CRBPTR Register Definition Table 21-25. CRBPTR Field Descriptions Bits Name Description 0–28 CRBPTR The CRBPTR register is internally written by the DMA module. The value increments by eight (bytes) each time a descriptor is read from memory. 29–31 — Reserved 015 16 25 26 31 R 0 0 0000 0000 0000 00 MRBL 0 0000 0 W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x2_6340 Figure 21-27. MRBLR Register Definition Table 21-26. MRBLR Field Descriptions Bits Name Description 0–15 — To ensure that MRBL is a multiple of 64 these bits are reserved and must be cleared. 16–25 MRBL Maximum receive buffer length. The number of bytes that the FEC receiver writes to the receive buffer. The MRBL register is written by the user with a multiple of 64 for all modes. The FEC can write fewer bytes to the buffer than the value set in MRBL if a condition such as an error or end-of-frame condition occurs, but it never exceeds the MRBL value; therefore, user-supplied buffers must be at least as large as the MRBL. Note that transmit buffers can have varying lengths by programming TxBD[Data Length], as needed, and are unaffected by the MRBLR value. MRBLR is not intended to be changed dynamically while FEC is operating. Change MRBLR only when the FEC receive function is disabled. 26–31 — To ensure that MRBL is a multiple of 64 these bits are reserved and must be cleared. |
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