MPC8540 datasheet(1178/1302 Pages) FREESCALE

1178 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-38

Freescale Semiconductor

10/100 Fast Ethernet Controller

reduce the likelihood of lost packets and packets leaking through the back pressure mechanism,

BPNB must be set.

The FEC drops carrier (ceases transmitting preamble) periodically to avoid excessive defer

conditions in other stations on the shared network. If while applying back pressure, the FEC is

requested to send a packet, it stops sending preamble, and waits one IPG before sending the packet.

BPNB applies for any collision that occurs during the sending of this packet. Collisions for packets

while THBP is asserted are counted. The FEC does not defer while attempting to send packets

while in back pressure. Again, back pressure is nonstandard, but can reduce the flow of receive

packets.

21.5.3.6 MAC Registers

This section contains descriptions of the MAC registers.

21.5.3.6.1 MAC Configuration Register 1 (MACCFG1)

The MACCFG1, shown in Figure 21-30, is written by the user.

Table 21-29 describes the fields of the MACCFG1 register.

Soft_Reset

00000

Reset_

Rx_MC

Reset_

Tx_MC

Reset_

Rx_Fun

Reset_

Tx_Fun

Reset

0000_0000_0000_0000

24 25

00000 Loop_

Back

Rx_Flow Tx_Flow

Sync’d_

Rx_EN Rx_EN

Sync’d_

Tx_EN

Reset

0000_0000_0000_0000

Offset

0x2_6500

Figure 21-30. MACCFG1 Register Definition

Table 21-29. MACCFG1 Field Descriptions

Bits

Name

Description

Soft_Reset

0 Default

1 Setting this bit puts all modules within the MAC in reset.

1–11

—

Reserved

Reset_Rx_MC

0 Default

1 Setting this bit puts the receive MAC control block in reset. This block detects control

frames and contains the pause timers.

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