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AD7794 Datasheet(PDF) 9 Page - Analog Devices

Part # AD7794
Description  Low Power, 24-Bit Sigma-Delta ADC with In-Amp and Embedded Reference (6 Channel)
PDF  21 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7794 Datasheet(HTML) 9 Page - Analog Devices

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Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 9
TIMING CHARACTERISTICS8, 9
Table 2. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise
noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK High Pulsewidth
t4
100
ns min
SCLK Low Pulsewidth
Read Operation
t1
0
ns min
CS Falling Edge to DOUT/RDY Active Time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
t210
0
ns min
SCLK Active Edge to Data Valid Delay11
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
t512, 13
10
ns min
Bus Relinquish Time after CS Inactive Edge
80
ns max
t6
100
ns max
SCLK Inactive Edge to CS Inactive Edge
t7
10
ns min
SCLK Inactive Edge to DOUT/RDY High
Write Operation
t8
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time11
t9
30
ns min
Data Valid to SCLK Edge Setup Time
t10
25
ns min
Data Valid to SCLK Edge Hold Time
t11
0
ns min
CS Rising Edge to SCLK Edge Hold Time
8 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
9 See Figure 2 and Figure 3.
10 These numbers are measured with the load circuit of
Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
11 SCLK active edge is falling edge of SCLK.
12 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of
Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the
timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
13
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.



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