Preliminary Technical Data

AD7794

REV.PrE 6/04 | Page 17

Bit Location

Bit Name

Description

CLK1

CLK0

ADC Clock Source

0

0

Internal 64 kHz Clock, Internal Clock is not available at the CLK pin

0

1

Internal 64 kHz Clock. This clock is made available at the CLK pin

1

0

External 64 kHz Clock used. The external clock can have a 45:55 duty cycle.

1

1

External Clock used. This external clock is divided by 2 within the AD7794. This

allows the user to supply a clock which has a duty cycle worse than a 45:55 duty

cycle to the AD7794, for example, a 128 kHz clock.

MR5

0

This bit must be programmed with a Logic 0 for correct operation.

MR4

CHOP-DIS

This bit is used to enable or disable chopping. On power-up or following a reset, CHOP-DIS is cleared so

chopping is enabled. When CHOP-DIS is set, chopping is disabled.

MR3-MR0

FS3-FS0

Filter Update Rate Select Bits (see Table 10).

Table 9. Operating Modes

MD2

MD1

MD0

Mode

0

0

0

Continuous Conversion Mode (Default).

In continuous conversion mode, the ADC continuously performs conversions and places the result in the data

register. RDY goes low when a conversion is complete. The user can read these conversions by placing the

device in continuous read mode whereby the conversions are automatically placed on the DOUT line when

SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to

0

0

1

Single Conversion Mode.

In single conversion mode, the ADC is placed in power-down mode when conversions are not being

performed. When single conversion mode is selected, the ADC powers up and performs a single conversion,

conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode.

The conversion remains in the data register and RDY remains active (low) until the data is read or another

conversion is performed.

0

1

0

Idle Mode.

In Idle Mode, the ADC Filter and Modulator are held in a reset state although the modulator clocks are still

provided

0

1

1

Power-Down Mode.

In power down mode, all the AD7794 circuitry is powered down including the current sources, power switch,

burnout currents, bias voltage generator and CLKOUT circuitry.

1

0

0

Internal Zero-Scale Calibration.

An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles

to complete when chopping is enabled and 1 conversion cycle when chopping is disabled. RDY goes high

when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle

mode following a calibration. The measured offset coefficient is placed in the offset register of the selected

channel

1

0

1

Internal Full-Scale Calibration.

The fullscale input voltage is automatically connected to the selected analog input for this calibration.

The full-scale error of the AD7794 is calbrated at a gain of 1 using the internal reference in the factory. When

a channel is operated with a gain of 1 and the internal reference is selected, this factory-calibrated value is

loaded into the full-scale register when a full-scale calibration is initiated.

When an external reference is selected at a gain of 1, an internal fullscale calibration can be performed. When

the gain equals 1, a calibration takes 2 conversion cycles to complete when chopping is enabled and 1

conversion cycle when chopping is disabled.

For higher gains, 4 conversion cycles are required to perform the fullscale calibration when chopping is

enabled and 2 conversion cycles when chopping is disabled.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is

placed in idle mode following a calibration. The measured fullscale coefficient is placed in the fullscale

register of the selected channel.

Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a

system full-scale calibration can be performed.