AD7794

Preliminary Technical Data

REV.PrE 6/04 | Page 16

STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x88)

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register.

SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The

number in brackets indicates the power-on/reset default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1)

ERR(0)

NOREF(0)

0(0)

1(1)

CH2(0)

CH1(0)

CH0(0)

Table 7. Status Register Bit Designations

Bit Location

Bit Name

Description

SR7

RDY

Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

after the ADC data register has been read or a period of time before the data register is updated with a

new conversion result to indicate to the user not to read the conversion data. It is also set when the part

is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin

can be used as an alternative to the status register for monitoring the ADC for conversion data.

SR6

ERR

ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written

to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,

underrange or the absence of a reference voltage. Cleared by a write operation to start a conversion.

SR5

NOREF

No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage

that is below a specified threshold. When set, conversion results are clamped to all ones.

Cleared to indicate that a valid reference is applied to the selected reference pins.

The NOXREF bit is enabled by setting the REF_DET bit in the Configuration register to 1. The ERR bit is

also set if the voltage applied to the selected reference input is invalid.

SR4

0

This bit is automatically cleared.

SR3

1

This bit is automatically set.

SR2–SR0

CH2–CH0

These bits indicate which channel is being converted by the ADC.

MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)

The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the oper-

ating mode, the update rate and the clock source. Table 8 outlines the bit designations for the mode register. MR0 through MR15 indicate

the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets

indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.

MR15

MR14

MR13

MR12

MR11

MR10

MR9

MR8

MD2(0)

MD1(0)

MD0(0)

PSW(0)

0(0)

0(0)

0(0)

0(0)

MR7

MR6

MR5

MR4

MR3

MR2

MR1

MR0

CLK1(0)

CLK0(0)

0(0)

CHOP-DIS (0)

FS3(1)

FS2(0)

FS1(1)

FS0(0)

Table 8. Mode Register Bit Designations

Bit Location

Bit Name

Description

MR15–MR13

MD2–MD0

Mode Select Bits. These bits select the operational mode of the AD7794 (See

Table 9).

MR12

PSW

Power Switch Control Bit.

Set by user to close the power switch PSW to GND. The power switch can sink up to 20 mA.

Cleared by user to open the power switch.

When the ADC is placed in power-down mode, the power switch is opened.

MR11-MR8

0

These bits must be programmed with a Logic 0 for correct operation.

MR7-MR6

CLK1-CLK0

These bits are used to select the clock source for the AD7794. Either the on-chip 64 kHz clock can be

used or an external clock can be used. The ability to use an external clock is useful as it allows several

AD7794 devices to be synchronised. Also, 50 Hz/60 Hz rejection is improved when an accurate external

clock drives the AD7794.